The is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance.
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The is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable `M' counter, 7-bit programmable `A' counter and the necessary control and latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external control from a suitable microprocessor.. It is intended to be used in conjunction with a two-modulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser. The NJ8821 is available in Plastic DIL (DP) and Miniature Plastic DIL (MP) packages, both with operating temperature range to 170°C. The NJ8821MA is available only in Ceramic DIL package with operating temperature range to 185°C.
Low Power Consumption Microprocessor Compatible High Performance Sample and Hold Phase Detector >10MHz Input Frequency ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS Input voltage Open drain output, pin 3 All other pins Storage temperature Storage temperature to 1150°C (DG package, to 1125°C (DP and MP packages, NJ8821)
Test conditions unless otherwise stated: ± 05V. Temperature range NJ8821 BA: +85°C DC Characteristics Characteristic Min. Supply current OUTPUT LEVELS Modulus Control Output (MC) High level Low level Lock Detect Output (LD) Low level Open drain pull-up voltage PDB Output High level Low level 3-state leakage current INPUT LEVELS Data Inputs (D0-D3) High level Low level Program Enable Input (PE) High level Low level Data Select Inputs (DS0-DS2) High level Low level AC Characteristics Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to MC Strobe pulse width, tW(ST) Data set-up time, tDS Data hold time, tDH Latch address set-up time, tSE Latch address hold time, tHE Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Output resistance, PDA Digital phase detector gain Value Typ. Max. Units Conditions Value Typ. 35 07 Max. 15 mA Units Conditions fosc, fFIN = 10MHz fosc, fFIN to 5V square wave
mVRMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, See note 4. ns See note 2. µs See Fig. µs ns See note nF k V/Rad
NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically. 4. Operation 15MHz is possible with a full logic swing but is not guaranteed.